Hi,
  Has anyone got some demo code that will initialise the 16F917's onboard LCD
controller for 1/3 mux, 1/2 bias mode?
  I've managed to get the backplanes to enable (using the startup sequence in
the datasheet), but the segment drive pins are jammed either low or Hi-Z
(can't tell which at the moment).

  The startup code I'm using starts by disabling all the analogue inputs, and
shuts down the comparator module - that's done by loading 0x07 into ADCON1
and CMCON. After that's done, all the I/O ports are set to input mode and the
buffers are loaded with 0x00. I know the startup code is working, because
I've traced the code with the ICD.

Here's my LCD init code:

main:
	dbankif	LCDPS					; Set up LCD prescaler
	movlw	b'00000000'
	movwf	LCDPS

	dbankif	LCDSE0					; Enable all LCD segment outputs
	movlw	0xff
	movwf	LCDSE0
	movwf	LCDSE1
	movwf	LCDSE2
	
	dbankif	LCDCON
	movlw	b'01001010'				; 1/3 multiplex, LFintosc, SLPen
	movwf	LCDCON

	dbankif	LCDDATA0
	movlw	0xFF					; Turn all segments on
	movwf	LCDDATA0
	movwf	LCDDATA1
	movwf	LCDDATA2
	movwf	LCDDATA3
	movwf	LCDDATA4
	movwf	LCDDATA5
	movwf	LCDDATA6
	movwf	LCDDATA7
	movwf	LCDDATA8
	movwf	LCDDATA9
	movwf	LCDDATA10
	movwf	LCDDATA11

	dbankif	PIR2
	bcf		PIR2,		LCDIF		; Clear LCDC interrupt flag
	dbankif	PIE2
	bcf		PIE2,		LCDIE		; Disable LCDC interrupts

	dbankif	LCDCON
	bsf		LCDCON,		VLCDEN		; Turn on the Vlcd (bias) pins
	bsf		LCDCON,		LCDEN		; Enable the LCD controller
	goto $		; halt the cpu

For reference, DBANKIF == BANKSEL.

Can anyone see anything wrong with this code? Near as I can tell, I'm
following the procedures in the LCDC section of the datasheet exactly, but it
still won't work!

It's set to 1/3 bias because when I ran the code through MPLAB-SIM, LCDPS bit
6 (BIASMD) remained locked low no matter when I set it. The same thing
happened when I ran the code on the ICD - bits 5 and 6 of LCDPS stuck at
zero.

The only other thing I've noticed is that although the PIC is configured to
use the INTOSC, it seems to be running of the LPINTOSC instead. ICD2 Memory
Update cycles are painfully slow (on the order of 30 seconds every time the
ICD single-steps or stops at a breakpoint). Weird thing is, OSCCON is
supposed to default to a setting that would make the chip run at 4MHz.

The LCD I'm using is an 8-digit calculator LCD that appears to have been used
with an RCL Semiconductors C7171C2 controller IC. That chip used a 1/3
multiplex, 1/2 bias drive waveform with a Type B waveform.

Thanks.
-- 
Phil.                              | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem@dsl.pipex.com              | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/          | Panasonic CF-25 Mk.2 Toughbook
... Assumption is the mother of all screwups...
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist