Vasile Surducan wrote:
> I need to design a TQFN-56 package with exposed (thermal) pad and a
> number of through holes on this exposed pad between layers 1 and 16.
> Drawing the TQFN is ok. Drawing the through metalised holes is ok
> using vias. But in the library can't coexist vias on rectangles or
> polygons without generating error in DRC when component is used.
> The exposed pad needs a large numbers of holes and open copper
> surfaces without termals (while the other power planes on layers 1, 2,
> 3 and 16 needs thermals).
> So, how can be done in library without using restrict tricks and
> multiple planes in the board ?

I don't think there is an easy way to do this.  You might be able to do
something manually with drills and filled areas, but I don't think there is
a way to avoid all the resulting DRC errors.


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