The datasheets and ap note are a bit unclear on how CCP compare mode works
when it's driving a pin.

>From AN594, we find:

In Compare mode, the 16-bit value of Timer1 is
compared to the CCPRxH:CCPRxL registers. When
these registers match, the S/W configured event
occurs on the CCPx pin. The events that can be S/W
selected are:
=95 Clear CCPx pin on match
=95 Set CCPx pin on match
=95 Generate S/W interrupt (CCPx pin unchanged)
=95 Trigger special event (CCPx pin unchanged)
- CCP1 clears Timer1
- CCP2 clears Timer1 and sets the A/D=92s
GO/DONE bit
The CCPxM3:CCPxM0 control bits, in register
CCPxCON, configures the operation of the CCP
module. The compare function must have the data
direction of the CCPx pin configured as an output, if the
compare event is to control the state of the CCPx pin.


So, I can tell the CCP to set or clear a pin on a match. Let's say I tell
it to set the pin on the match. How do I clear the pin? Or is only high
DURING the match and low for all other timer values? Since a match also
sets an interrupt flag (18f252 page 120), does, perhaps, clearing the
interrupt flag return the output pin to the "non-matched" state? That same
page also says that clearing CCPCON1 forces the compare output latch to
the default low output level. Is this the way to change the state of the
pin back to the non-matched state?

Seems like this could be a little more clear in the datasheets or ap
notes. Anyway, any info appreciated!

Thanks!

Harold



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