In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Coriolis wrote:

Wow, thats a great SRAM, its 15ns is the cycle time and not just access time. Micheal seems to have covered the bases, the timing seems to be ok, but the /WE has to be toggled for each write, the note says either /CE or /WE has to be high during the address change. In the timing diagrams whenever a value is a minimum time of 0, this means the time can change at the same time, but the order must be preserved (the transition must occur in the order described either at the same time or some time later in the proper sequence (ie /WE can go high at the same time as the address change, but it must be high during the address change. I know this a slightly confusing).

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