David Van Horn wrote
>I've put a logic analyzer on both systems, everything seems right, 
>nothing's anywhere near any timing issues (THAT ARE IN THE DATA SHEET), 
>and by all appearances it should be working.

This is long shot but on an nRF905 I found that the rest state of the 
SPI clock was important. Although the data sheet doesn't say so 
explicitly I found I couldn't initialise the device when the clock was 
resting high when CSN went low - even though data was stable and clocked 
on the correct edge. I wouldn't expect an LA to show any difference in 
the data it collected.

-- 
Martin
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist