> I'd be tempted to suspect a bad solder joint (ie, the signal may not
> be getting into the chip, only near it) and ground and power issues.

Yes. These MLF packages are a bit frustrating that way, there's nowhere
really to probe other than on the solder joint, which isn't the same as
the old trick of probing on the DIP chip's leadframe rather than on the
PCB or socket.  I've reflowed the joints though, and examined under a
microscope, and they appear to be wetting the chip pads fine.

> Beyond that, have you matched the capacitors on the prototype closely
> to the working version?  (value, voltage, ESR, composition)

Yes. 

> I understand that these chips are rather sensitive to layout issues as
> well.  Are you using the layout in the data sheet, or from a working
> design?

We are just talking about the logic signals at this point. Our RF layout
is different, but we believe we know what we are doing on that side :)

Very puzzling..

My biggest gnawing suspicion is that there's 18 months between the chips
that work, and the ones that don't.  I haven't seen any documentation on
errata, but that doesn't mean there isn't any.
  


-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist