In SX Microcontrollers, SX/B Compiler and SX-Key Tool, hmsmith wrote: First, to answer your question, the RTCC block diagram on page 24 of the SX20/28 datasheet shows that an XOR gate can invert the external RTCC pin based on the RTE_ES bit in the option register. This XOR gate is before the multiplexer (controlled by the RST bit) that selects internal or external clock for the RTCC. Thus, the XOR gate and the RTE_ES bit does not affect the internal clock edge. However, if you are driving the SX cpu with an external clock, there is nothing to stop you from connecting the incomming clock to both the OSCIN and RTCC pins, which would allow you to change the RTCC clock phase. The problem that I hane with your question is it ignores the fact that the SX cpu is not affected in any way by which clock edge that you use. The SX series of processors execute instruction at the rate of one instruction per clock cycle. Whether you use the RTCC as a readable register or to generate an interrupt, the CPU will always read/respond to the value as synchronized to the CPU clock on that cycle. The datasheet does not specify the point in a cycle at which, for example, an input pin is sampled, but you can assume that it will be consistant. The following code samples assume that the cpu clock is connected to Port B pin 0: LOOPHIGH: sb portb.0 ; Test the pin, skip if pin high jmp LOOPHIGH ; repeat until the pin is high LOOPLOW: snb portb.0 ; Test the pin, skip if pin low jmp LOOPLOW ; repeat until the pin is low Even though the pin is continiously toggling, one of these loops will always drop through immediately, and the other will loop forever. If you invert the phase of the CPU clock as connected to the input pin, the only thing that will change is which loop drops through and which loops for ever. Assuming that you are trying to clock the SX cpu is sync with the SDRAM and then generate the RD, WR etc. control signals in s/w on the SX cpu, I suggest that you clock the SDRAM at half the CPU clock. You could do this with an external FlipFlop, or (if you use the SX48/52) with one of the counter/timers. Assuming, for the following example, that the SDRAM clock is connected to Port B pin 0, and you want to drive RD low (Port B pin 1) on one phase of the SDRAM clock and WR low (Port B pin 2) on the next phase: SDRAMCLKLOW: nop snb portb.0 ; Test the pin, skip if pin low jmp LOOPLOW ; repeat until the pin is low clrb portb.1 ; drive RD low clrb portb.2 ; drive WR low If the SDRAM clock on Port B pin 0 is low when the CPU executes the SNB instruction, the skip will be executed (taking 2 CPU clocks, 1 SDRAM clock), then the RD pin will go low followed by the WR pin one CPU clock later. Since one CPU clock equals one half SDRAM clock, WR changes on the opposite SDRAM clock phase to RD. If the SDRAM clock on Port B pin 0 is high when the CPU executes the SNB instruction, the skip will not be executed (1 CPU clock) so the jump will be taken (3 CPU clocks) followed by the NOP (1 CPU clock). Now the skip test will be repeated. Since we have executed 5 CPU since the previous test, the SDRAM clock should now be on the opposite phase and therefore the skip test will be true and the skip will be taken. I hope this helps you with your project. When interfacing the SX CPU with high speed hardware, it is often important to count the number of CPU clocks between each change in an external signal. The SX datasheet does not indicate the delay between an I/O instruction (eg clrb portb.1) and the actual change of the pin. To make my sample code work as you wish you may need to use a scope or logic analyser to fine tune the code. Since you cannot control the cpu clock to output time, it may be impossible to meet the setup and hold times required for your SDRAM without further dividing the SDRAM clock. Regards, Hugh Note that the nop is important. ---------- End of Message ---------- You can view the post on-line at: http://forums.parallax.com/forums/default.aspx?f=7&p=1&m=97863#m98180 Need assistance? Send an email to the Forum Administrator at forumadmin@parallax.com The Parallax Forums are powered by dotNetBB Forums, copyright 2002-2005 (http://www.dotNetBB.com)