This may be of interests to some people here. The designer
is our fellow PIClist memeber Shawn Tan.

Regards,
Xiaofan

http://www.opencores.org/projects.cgi/web/ae18/overview

AE18: Overview

Details
Name: ae18
Created: 07-Aug-2003 11:10:03
Updated: 11-Mar-2005 12:52:43
CVS: no files in cvs

Other project properties

Category :: Microprocessor
Language :: Verilog
Phaze :: Design done
Development status :: Production/Stable

 Project maintainers

Shawn Tan Ser Ngiap

Description

The AE18 is a clean room implementation of the Microchip PIC18 series
CPU core using information from the PIC18C documentation from their
website. It is cycle and instruction compatible to the PIC18 except
for the TABLE instructions that are single cycle instructions on the
AE18.

This is just a CPU core that is capable of moving and manipulating
data to and from memory. It does not have any peripherals nor
interrupt controllers although support for both high and low level
interrupts are provided in the ae18_power unit. Any peripherals and
their respective registers will have to be mapped to the data memory
space.

PIC, Microchip, etc. are Trademarks of Microchip Technology Inc. I
have no idea if implementing this core will or will not violate
patents, copyrights or cause any other type of lawsuits. I provide
this core AS IS, without any warranties.

Features

Shared 16Mb memory space (unified instruction/data memory).
8bit external data bus.
Instruction and Cycle compatible except for single cycle TABLE instructions.
Full 24bits instruction memory (8bit PCLU).
Full 16bits data memory (8bit BSR and FSR#H).
Custom user peripheral/interrupt controllers.

Status

Synthesizable CPU core on Spartan2-200 with 60k gates @ 60 Mhz..
Fully tested in software simulation running code compiled with GPASM.
Not prototyped on FPGA as I don't have one (any donations/sale?)

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist