> Hi to all,
>
> I am having hard time to make my Xilinx demo board working and
> I am new to VHDL.  I was wondering if some one can check my
> test code. All I am trying to do is to turn  4 LEDs on and it doesn't work
> any help?
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity test is
>      port( LED_0,LED_1,LED_2,LED_3: OUT STD_LOGIC);
> end test;
>
> architecture behavior of test is
>      begin
>      LED_0 <= '0';
>      LED_1 <= '0';
>      LED_2 <= '0';
>      LED_3 <= '0';
> end behavior;

Seems reasonable but then I am tired right now.

It synthesizes, places and routes?  The "gate-gobbler" isn't throwing any
warnings?

Is your UCF file correct, are the pin assignments correct?

You don't say above but are the LEDs are expected to turn on when you sink
current?
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