On Wed, 2005-11-23 at 14:46 -0800, Andre Abelian wrote:
> Hi to all,
> 
> I am having hard time to make my Xilinx demo board working and
> I am new to VHDL.  I was wondering if some one can check my
> test code. All I am trying to do is to turn  4 LEDs on and it doesn't work
> any help?
> 
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> 
> entity test is
>      port( LED_0,LED_1,LED_2,LED_3: OUT STD_LOGIC);
> end test;
> 
> architecture behavior of test is
>      begin
>      LED_0 <= '0';
>      LED_1 <= '0';
>      LED_2 <= '0';
>      LED_3 <= '0';
> end behavior;

Don't see anything wrong off hand (although my VHDL isn't the best, MUCH
prefer verilog, WAY easier to understand for many people new to HDL),
have you confirmed the outputs you've declared are defined on the pins
you want? Assuming you're using ISE that would be your ucf file. In time
that's a file you'll modify by hand, but right now double clicking on it
will open iMPACT which will allow you to check your pin assignments.

Also, I'm not sure what version of Xilinx's ISE you're using, but if
you're using XST as your synthesis tool it's very likely you're pins are
being optimized out (XST is by default very agressive at eliminating
static nets). If all else checks out, change you're code to add an
input, tie that pin to ground, and assign your LED pins to that net, XST
can't optimize out that sort of config.

TTYL

-----------------------------
Herbert's PIC Stuff:
http://repatch.dyndns.org:8383/pic_stuff/

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist