> but I assumed that for higher speeds, I needed a very small error
> or no error at all

Error is relative to any speed - IOW 2% error at 300b is just as
good/bad at 115kb. 0% is the ideal, and you'll have no losses at
any speed for any length of packet. Where error becomes more
of a factor is as the packet lengthens. The slippage between the
UART sampling time/position and the bit centre is progressive and
cumulative and eventually, without correction (eg resetting the
UART at calculated and regular intervals), the UART and data
will get too far apart

> Well, according to my estimates, 7.3MHz is enough to do the kind
> of processing I'm gonna do, but I wanted to step up just to be sure

> Besides the additional power consumption, what other disadvantages
> there are in using the 14MHz crystal? (cost is irrelevant as this will
> never make production level quantities)

You may as well PLL the 7MHz up to 28MHz. Maximum common
crystal you could use with PLL on a 40MHz PIC would be 9.8304.
Don't know of any disadvantages, but you might want to consider
how the I/O interfaces at higher speeds (add or adjust delays for
capacitive loads for example). I can't think of any serious unfixable
problems I've ever had at 39-40MHz

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