Alan B. Pearce wrote:
>You should be able to find some messages in the Piclist.com archive, as I
>did ask the question there, be around three years ago now IIRC.

Thanks.  I've found a reply from you on this subject on 3rd October 2002 --
http://tinyurl.com/dtufz -- but without any links to its parent, so I'm not
sure of the exact context.

  >It's not a bug, there is no configuration that gives start
  >and stop bit interrupts in slave mode, only in master mode.

  ...

  The only place that implies these two slave modes never interrupt is in the
  description of the PIE register where it talks about the enabling of the
  SSP interrupt, and actually lists the items that will cause an interrupt.

This doe suggests that there's a problem with the interrupt on start and stop
bit mode, although it sounds as if the OP wasn't seeing *any* interrupts from
these sources, which is different from my own experience.  You refer to MSSP
rather than SSP, though, so there may be different issues with that module.  

  In the mean time I have implemented a timer interrupt using a spare timer
  to Monitor the P bit, and set my internal i2c idle flag back to idle when
  the P bit is set.

That sounds similar to the approach that I'm adopting.  I'd be interested to
hear whether it was effective.

Many thanks.
-- 
Ian Chapman
Chapmip Technology, UK
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