alan smith wrote :

> You mention the problems....enlighten me if you can?

That there is only one copy of the shadow regs used to
save/restore WREG, STATUS and BSR during the interrupt.
So only use "retfie, fast" from the high prio interrupt. The
low prio interrupt must save/restore the context much like on
the PIC16 line.

The shadow regs on the PIC18 can make short IRS's
considerable faster then on the PIC16, since context
saving is done "on th fly".

And since the PIC18 both runs faster, and have a "better"
instruction set, things can generally be done faster on them.

> The 
> problem I have right now, the target device is a 16F877 where 
> one function is acting as a frequency counter, where it uses 
> the rising edge interupt on port B0 to capture the incoming 
> pulses,

Aren't a timer used in "counter-mode" usualy used for that ?

> but there is a second interupt where it uses tmr0 
> and it works fine up to about 200Hz.
> I know the PIC is capturing the pulses up to the 
> frequency of interest (500Hz) by looking at the input 
> frequency and toggled an output port bit when it saw the 
> pulse (both on the analyzer showed they tracked).  At 
> frequencies approaching over 200Hz, it starts to deviate.  
> What I am thinking is that the intertupts are "fighting" each 
> other...whoever is first wins of course.  So if!

I'd look into using a timer as a counter instead to capture the
input pulses. That way one of the interrupt sources goes away.

Jan-Erik.



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