The biggest difference between FPGA and CPLD is the ability to do more floor planning and timing control.  CPLD's are like PAL, PEELs and PLDs where the timing, meaning the prop delays between registers are fixed.  They typically are cheaper as well.  
 
Writing code....VHDL, Verilog or SystemC.  I prefer verilog, but there is support for all of it out there.  
 
In anycase, the basic structures for HDL are alot the same for both CPLD's and FPGAs.  What you find are details with the specific devices that affect the upper level portion of the code, rather than the subroutines that do the work.
 
Follow the suggestions....Altera and Xilinx are the major players, with Lattic playing catchup and they do have some nice new parts (took the orca line if anyone remembers those parts)

 

		
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