>In PIC18, you can make use of the shadow registers.  BSR, STATUS and
>WREG all have their respective shadow register and during entering
>ISR, all instantaneous value are saved into the shadow registers. This
>is done automatically for you and you can use
>
>retfie    FAST
>
>to exit the ISR and all values are restored from their respective
>shadow registers.
> =20
>
This is fine. But what happens when a higher priority interrupt occurs=20
while the PIC is running the lower
priority interrupt handler code? The documentation does not talk about=20
having two sets of shadow registers:

"RETFIE s - Return from Interrupt. Stack is popped and Top-of-Stack=20
(TOS) is loaded into the PC. Interrupts are
enabled by setting either the high or low priority global interrupt=20
enable bit. If =E2=80=98s=E2=80=99 =3D 1, the contents of
the shadow registers WS, STATUSS and BSRS are loaded into their=20
corresponding registers,
W, STATUS and BSR. If =E2=80=98s=E2=80=99 =3D 0, no update of these regis=
ters occurs=20
(default)."

So I need to save W, STATUS and BSR in the low-priority handler and use=20
the shadow registers in the high-priority handler.
If interrupt priority levels are enabled, using "RETFIE FAST" in the low=20
priority interrupt handler is a programming error.
Am I right?

Les

--=20
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