>???  So what is the point of the "enable" bit?  The
>datasheet says "The TMR0 interrupt is generated when
>the TMR0 register overflows from FFh to 00h.  This
>overflow sets bit TMR0IF.  The interrupt can be
>masked by clearing bit TMR0IE."  I take this to mean
>that the TMR0IF interrupt would not be set on overflow
>(of the TMR0 counter/register) if TMR0IE is cleared.

I think you are forgetting about how the hardware works.

The timer counts, and on overflow (underflow?) sets the TMR0IF flag. This
occurs if the counter is counting irrespective of the state of the TMR0IE
bit. The only way to stop the TMR0IF flag being set is to stop the counter
totally.

The TMR0IE bit is used to gate the state of the TMR0IF bit into the
interrupt logic. The TMR0IF bit can still be polled by the software even if
the interrupt is not enabled.

The same is true for all cases where there is both F and E bits. The E bit
only gates the state of the F bit through to the interrupt logic.

Now about those 1000 lines ... ;)

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