Olin Lathrop wrote :

> HOWEVER, the target circuit must usually be off when 
> programming with the EasyProg since it assumes it
> is controlling the target Vdd.  I just checked,
> and the two particular PICs you mentioned use the Vdd before 
> Vpp sequence.
> This means you might get away with leaving the target powered during
> programming, but I haven't tried this and it's out of spec as 
> far as I'm concerned.

Hm, the Vdd line on the RJ12 socket on the Q-P is connected
the the main 5V rail on the board, right ? So when E-P "manage"
the Vdd line (through the "VDD18" rail), it is powering the
whole Q-P on and off, not ?

What if I just don't connect the Vdd line in the cable
between the two RJ12-sockets ? Just leaving GND/PGD/PGC/Vpp ?

Or, given the current setup (one E-P and one Q-P-01) what
would be your recomendation regarding powering of the the
boards and the re-programing of the chip in the 28-pin socket ?

Maybe I'd try to dig up a power suppy that matches the power
spec of the Q-P, I think I have a 15V supply around (old
laptop PSU). Would that make things easier/safer ?

I understand the problem with the diod bridges and the
ground line, thanks for pointing that out.
So, if running them on the same supply, connect ground
*after* the bridges, and the positive supply the regular way.

Regards, and thanks for the support !

Jan-Erik.



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