In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Coriolis wrote:

Thanks for the indepth explanation Micheal, it seems the upshot is, if you make sure you don't read and write the same register in a row, and you can ensure the input pins do not transistion near the clock edge, you should be able to operate with the /SYNC option off. I did this with a design where a CPLD and the SX were in 25MHz communication with each other (max speed for full cycle of on and off), I noted which clock edge the SX did its clocking on, and programed the CPLD to do its transitions on the opposite edge, I was thinking in terms of minimum setup and hold times, but I was unaware the general term was metastability (heard of the term but always thought of it in terms of clocking a slowly moving input where the value was between the accepted high and low values). Setting the inputs to Schmiddt trigger may help keep you out of this situation, but this is a guess.

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