I don't think the opto does any good. I use them only where there's
actually some isolation required.

What's the size of the resistor in series with the gate? You'll have
substantial "Miller Effect" gate capacity, so any series resistance will
slow the gate down, causing the FET to not be saturated.

The FET will only get hot when it's dissipating power. The power being
dissipated is Vds*Id. The problem area is generally that the drain is
being pulled out of saturation when the FET is on (giving you both Vds and
Id). Ideally, when the FET is on, Vds is very low and Id is whatever is
required.

I'd watch the drain voltage on a scope to see what's going on. Also, have
a look at the gate voltage. If you run 100% duty cycle, I'd suspect the
gate to rise to some plateau, then stay there for a while as the drain
voltage falls (Miller Effect), then the gate goes to the PIC output
voltage. On the drain, the voltage should fall very quickly, then stay
down as long as the solenoid is on. If you find the drain voltage starting
to rise, the FET is being pulled out of saturation. The solenoid current
(since the solenoid is an inductor) will (ignoring the inductance change
due to slug movement) will linearly ramp up until the core saturates, then
linearly ramp up faster (due to lower permeability) until it is limited by
resistance. If, as you mention, the solenoid current gets too high if held
for a long period of time, you can PWM it, as you're doing. The trick is
to PWM it at a low enough frequency so you don't have tremendous gate
drive requirements (gate current), and high enough so the noise is not
bad.

Finally, look at the datasheet on the FET. It should show Id vs Vgs. What
current SHOULD you get through the FET when the gate is driven with the
voltage you're driving it with (probably 5V out of a PIC)? Different FETs
have different Id vs Vgs curves.

So, like Google, an oscilloscope is your friend. Look at Vg and Vd...

Good luck!

Harold

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