PicDude writes about doing a software I2C master:
...
 > My questions...
 > (1) 2 modes are mentioned -- 100khz (Std.) and 400khz (Fast).  Different 
 > timings are specified for each mode.  How are modes switched/selected?  I 
 > expect that it would need to be selected, since 2 different values are 
 > specified for parameter "Taa" (Output valid from clock, max times=3500 and 
 > 900ns).  This tells me that the device will have it's output valid after a 
 > maximum of so much time, and it's based on the mode.

	I'm responding without looking at the data sheet first, so
take this for what it is worth.

	"Standard" and "Fast" are terms from the I2C spec.  (The spec
is worth reading.  Phillips provides a PDF version on their website
somewhere.)  These are levels of performance for manufacturers of
slave devices to advertise that their parts meet.  An interface can be
run "fast" only if there are no devices on the bus that are only
guaranteed to meet the "standard" timing parameters.  Part of the
charm of I2C is that slaves are not required to do any timing
(W.R.T. the bus), they are only required to be at least as fast as the
numbers in the spec.

	So far as I know, devices don't have modes.  They are
available in versions, e.g.; 24LC512, 24AA512, 24FC512, some of which
may not meet "fast" timing, and some of which do (all must meet or
exceed "standard" timing or they're not officially I2C devices).
Whether a particular version is guaranteed to meet "fast" timing may
depend on supply voltage, or upon temperature, so if you're system Vcc
is less than, for example, 2.5V, you may be forced to use "standard"
timing.

 > 
 > (2) What exactly does that Taa mean -- I interpret it to mean that after the 
 > specified time, the EEPROM's return data will definitely be valid.  But is 
 > there a limit on this, or does the data stay on the line as long as there is 
 > no additional changes to the SCL line?

	No limit.  From the slave's point of view, the interface is
static.  It will make no further change on its own.  SCL must change
to move its state forward.

 > (3) Most parameters don't have a maximum time.  Does this mean my code can 
 > write some bits in the middle of a transaction, run off and do other things 
 > and come back a minute later and pick up where it left off and all will be 
 > hunky-dory?

	Yup.  Parameters that are limits on the master generally only
have minimums, except Fclk, which has a maximum, but that's really a
minimum limit on clock period.  The slave is responsible for being
able to deal with things that are that fast.  You can even look at TAA
as a minimum for the master: the minimum time that it should wait
before sampling the data (beginning of setup time of the master's
input latch that will be clocked on rising SCL, if that's how you
choose to do it - a software implementation should simply sample with
SCL high and let clock low time requirements govern).

	The exception is Tr and Tf, which apply to both master and
slave, and also the system design (bus wiring capacitance, pull up
choice, driver capabilities).  Note that for a single master system
you can use totem pole drive for SCL.

	I hope this helps.

							Bill

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