Olin Lathrop wrote:

> Stef Mientki wrote:
>
>> I've done some tests with both SSPSTAT bit 6,7
>> and my raw conclusion is that the effects of bit 7 are marginal.
>
>
> Actually there is a noticeable difference in the falling edges in most
> cases.  This is exactly what you'd expect.  The difference only looks
> marginal in your pictures because they weren't set up well to look for 
> the
> effect, but it's still visible.

I just measured the fallig edge in my setup (just 1 I2C eeprom, so let's 
say 20pF),
SSPTAT<7> = 0, slew rate control enabled : 70nsec
SSPTAT<7> = 1, slew rate control disabled : 15nsec
As the fall times of I2C are specified at a maximum of 300 nsec,
I still would say the difference is very marginal.

Another way of looking at it,
If you achieve the real I2C specifications (which is probably the goal 
of Microchip),
you can transfer at 3.4 MHz with a bus load of 100 pF.
As most I2C devices, just have a maximum of 1 Mhz,
and if our I2C devices are on a well designed board,
creating a maximum of say 30..  50pF,
timing can never be a problem.

So in general there's just one element valid argument (given by Patrick),
always enable slew rate control, to improve the EMC performance.

Stef

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