>Michael Rigby-Jones wrote:
>

>>Slew rate refers to the maximum rate of change of voltage (which 
>>essential determines the rise/fall time of the clock/data 
>signals), and 
>>the PIC can only control this on it's outputs.  I don't know the 
>>specifics of exactly how it controls the slew rate, I guess some kind 
>>of compensation is applied around the pins output driver.
>>
>>The electrical specifications in the back of the PICs 
>datasheet should 
>>give the relevant rise/fall times.
>>  
>>


Stef Mientki replied:

>Yes, and there's is nothing depending on SSPSTAT<7>,
>so therefor I concluded it doesn't do anything with the slew rate.
>
>The only parameters that I could find,
>which are *possible* involved in SSPSTAT<7> are
>D034 ./ D034A and D044 / D044A
>D034/D044 specifies the input high/low voltage range on RC3/RC4 with 
>smitt-trigger enabled
>D034A/D044A specifies the input high/low voltage range on RC3/RC4 with 
>smitt-trigger disabled (also called SMbus)
>

What device are you refering to? There are some differences between PIC's.  

Using the 16F877 datasheet for example, the SMP bit controls wether or not slew rate limiting is applied in high speed (400KHz) mode.  If you refer to the "I2C Bus Data Requirements" under the Electrical Characteristics section, you will see "SDA and SCL Rise time" and "SDA and SCL Fall time".  For each parameter, a separate figure is given for 100KHz and 400KHz (high speed mode).  If you use the MSSP in high speed mode but with slew rate limiting disabled, you would (I think) get the same rise/fall times as the 100KHz mode.

The I2C/SMBus input threshold levels are controlled by the CKE bit and have nothing to do with slew rate.

Regards

Mike

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