In SX Microcontrollers, SX/B Compiler and SX-Key Tool, kmonsx wrote:

I was looking at the datasheet([url=http://www.ramtron.com/lib/literature/datasheets/FM25256ds_r2.1.pdf]link here[/url])for the FM25256 and wondered if someone can help here.

Page 7, under Write Operation, the datasheet linked above says, "[.....][2]Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks.[/2]"

As long as I don't raise CS to terminate the Write operation, can I simply stop sending a clock on SCK until I have more data to write, and then start the clock back up to continue writing where I left off?  I did read the errata concerning suspending SCK in the middle of the data byte --- but that won't apply to me.  I'm writing whole bytes, so I'd never suspend the clock in the middle of the write of a single byte.

My main concern is that the WREN plus the write op-code including the address is really a ton of data, relatively speaking, and I'd hate to have to resend that for each and every byte I needed to write just because they were separated in time.

Page 2, under the SCK pin Description, "[2]Since the device is static, the clock frequency may be any value between 0 and 15 MHz and may be interrupted at any time." seems to confirm what I'm guessing, but I really have no experience here.[/2]

And the related question is, if I can do this, what's HOLD for? :)  I'm trying to make this as simple and straightforward implementation as possible using the fewest number of pins.  I'd be happy with the 3-pin minimum!

[2]Thanks.[/2]

[2]Keith[/2]

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