>-----Original Message-----
>From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] 
>Sent: 19 August 2005 15:19
>To: Microcontroller discussion list - Public.
>Subject: Re: [PIC]: I2C & SPI shared bus
>
>
>I've posted this before, but still have had not time to play 
>with it myself.
>
>You can separate the SCK/SCL signals with 2 and gates and an 
>inverter as the following lifelike a la Picasso ASCII art shows:
>
>PIC                           -----
>SCL/SCK --+-------------------|    \
>pin       |                   |     |----- SCKOUT
>          |   I/O pin -----+--|    /
>          |                |  -----
>          |                |
>          |                V  <- inverter
>          |                o
>          |                |  -----
>          |                +--|    \
>          |                   |     |----- SCLOUT
>          +-------------------|    /
>                              -----
>
>If I/O pin is high, then SCKOUT is active and if I/O pin is 
>low, then SCLOUT is active.
>
>I believe that those AND gates need to have open collector 
>outputs, but someone with more knowledge of the I2C/SPI than 
>me will need to confirm or deny this fact.
>
>In theory, the above works really well, but like I said, I 
>still have not had time to play with this myself so I can't 
>guarantee it will work.  If you do try it and it works, let us know.
>
>Good luck.

It should work, the only snags I can see are the use of an extra port pin, and the I2C can only be a master, not a slave and it cannot supprt clock stretching as a master.

Regards

Mike

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