I've posted this before, but still have had not time to play with it myself.

You can separate the SCK/SCL signals with 2 and gates and an inverter as
the following lifelike a la Picasso ASCII art shows:

PIC                           -----
SCL/SCK --+-------------------|    \
pin       |                   |     |----- SCKOUT
          |   I/O pin -----+--|    /
          |                |  -----
          |                |
          |                V  <- inverter
          |                o
          |                |  -----
          |                +--|    \
          |                   |     |----- SCLOUT
          +-------------------|    /
                              -----

If I/O pin is high, then SCKOUT is active and if I/O pin is low, then
SCLOUT is active.

I believe that those AND gates need to have open collector outputs, but
someone with more knowledge of the I2C/SPI than me will need to confirm or
deny this fact.

In theory, the above works really well, but like I said, I still have not
had time to play with this myself so I can't guarantee it will work.  If
you do try it and it works, let us know.

Good luck.


-Mario


> Olin Lathrop wrote:
>
>>> Then during SPI transfers, there shouldn't be anything that resembles a
>>> valid I2C transaction on the bus.
>>
>> Huh!!?.  You are practically guaranteed to get some bus start and bus
>> stop sequences.
>
> Since SPI isn't really well-defined WRT data changes vs. clock changes,
> this may or may not work. If any of your SPI devices requires you to
> configure the SPI master so that there are data changes while the clock is
> high or may produce such changes as slave, you are practically guaranteed
> to create an IIC start condition while you are sending SPI data.
>
> If OTOH you can guarantee that all SPI data transitions happen while the
> clock is low, you can get away with it; in this case there won't be an IIC
> start condition during SPI transfers.
>
> I've done it before, and it can work. But it depends on the SPI devices
> and
> their data transition timing.
>
> Gerhard
> --
> http://www.piclist.com PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist