In SX Microcontrollers, SX/B Compiler and SX-Key Tool, drnow wrote:

I am trying to get an ISR to execute 1440 times per second.  That would be every 694.4 usec.  Using the prescaler set to 1:256, the RTCC will be incremented once every 256 cycles.  If the clock is set at 50 MHz, that would be 5.12 usec.  Dividing the 694.4 by 5.12 yields 135.6, rounded to 136.  So, if the interrupt occurred after the (prescaled) RTCC is incremented 136 times, we would be pretty close (5.12 * 136 = 696.3 usec).

But here's the question:  at the end of the ISR, I presume you would need to use an retiw to reset the RTCC to -136.  If I read the manuals correctly, that retiw would reset the prescalar.  If it does, the count of machine cycles monitored by the prescaler gets lost, so the length of the total time to the next ISR becomes unpredictable (+/-256 machine cycles).  It would be better if the program would exit the ISR just as the prescaler is rolling over, and retiw was executed at that time.  Then, everything would stay lined up with proper complete prescaler durations.

Any suggestions on how to do this?

James

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