> BTW I don't understand how you can have 72 osc cycles before 
> Vdd is applied.

The spec talks about the time between /MCLR logical high (so the chip is
released from reset) and /MCLR being at Vpp level (so the chip enters
programming mode). When too much time elapses between these two points
the chip start running. Apparently the programming hardware uses the
program counter, assumes it to be 0 on programming-mode-entry, without
resetting it.

This can of course only be an issue with the Vdd-before-Vpp sequence
(without the dongle), with Vpp-before-Vdd /MCLR is already at Vpp when
the chip is powered.

The F88 progspec is a bit peculiar, it indeed does not mention the
Vpp-first sequence, yet the /MCLR pin of the chip can be configured as
input, and it can be configured for internal oscillator. Maybe a
documentation error, or maybe this chip never needs the Vpp-first
sequence.

Wouter van Ooijen

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