Rob Hamerling wrote :

> I have set RA5/MCRL to digital I/O...

OK, so=20
the PIC "runs" as soon as Vdd is applied.

The Prog Spec says :

"Note:=20
The Osc must not have 72 osc clocks
while the device MCLR is between=20
VIL and
VIHH."

And also :

"Note: The MCLR pin should be raised from
below VIL to above the minimum VIHH
(VPP), within 250 =B5s of VDD rise."

(Or simply appying Vdd *after* Vpp.)

I thought that enabling internal-
MCLR
on *any* PIC also implied this requriment
in timing between Vpp=20
and Vdd.



> I inserted Wouters 'dongle' between Wisp628 and
> target=20
board, but that made no difference.

Not that the dongle must be able=20
to *fast* short
Vdd to GND and also fast release Vdd again.

So you=20
can't have to many uF's on the
breadboard.

A "few" uF's usualy works=20
for me.

You can't power the curcuit with something that
can't be=20
shortet to GND. A 7805 or 78L05
i usualy OK.

Some bench-labb-power-
supplys have
"slow start" after a short. That does not
work.

I've use=20
the dongle with success and also
one of my Wisp628 customers that=20
locked
himself out from a 12F.

What you see is exectly this, you can't=20
get the device
into programming mode, and the Wisp628
can't "see" it at=20
all.

So, try the dongle again. Be carefull with your caps
on the=20
breadoard.

Jan-Erik.




--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist