In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Coriolis wrote:

Thanks Peter, I had a feeling that was the case. 

I think I've got the module switching code down to 5 cycles (+1 if fsr needs to be set), I should be able to squeeze that in, the fast process is 3.57 MHz or a state transistion every 7 cycles, leaving 6 cycles between the trailing edge of the clock to the leading edge of the clock. Man I thought calculating the timing of NTSC was tricky, thats childs play compared to organizing a 3.57 MHz process, a 450 kHz process (1/8th speed of the faster process) and stuffing a bunch of support functions to perform data manipulations during the "dead space" while keeping the fast proccess a rock steady frequency. 

As I hinted, Im tackling it by writing the support functions, then lacing them with the fast and slow processes by hand, then stringing them in a fashion that the leading edge of the clock in the next module happens exactly 7 cycles after the previous module's last trailing edge of the clock. Ive thought about using a preprocessing framework to do the merging of the processes but I think that would take longer than doing it by hand. Does anyone know of a free generic, flexible preprocessor that is also easy to use?

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