In SX Microcontrollers, SX/B Compiler and SX-Key Tool, DigitalDj wrote:

Peter,

1. I take it that the SX will only require 1 I2C bus on the input and then the controlled I2Coutputs through the SX?

2. How does the I2C buss know if there are more than 2 LM4970 on a buss if all chips are set high except the 1 that is low to be addressed?

3. If memory is a problem how about going with option C with the CD4052 or CD4051 that paul has described?

4. Am i correct in saying there is no provisions for the address lines to the LM4970's?

I guess for now if it is a real problem i could always stick with individual addressing to the LM4970's, processing speed would be great enough to probably not see any difference. The other problem is i will need to learn to program the SX but i guess that's the fun of it!

Kevin

 



[quote="Peter Verkaik"]

The I2C bus is by definition half duplex. On a single I2C bus only one chip can be addressed

at any time. If you want to address multiple chips simultaneously, you must have multiple

I2C buses that are serviced simultaneously.

You could dedicate an SX28 chip as follows:

port A (pins ra.0 to ra.3) = serial port with TX,RX,RTS,CTS

Use a max232 to connect to PC comport.

This can connect to a USB to serial adapter to allow control via USB

port B (pins rb.0 to rb.7) = 4x I2C bus

port C (pins rc.0 to rc.7) = 4x I2C bus

This gives you 8 independent I2C buses so you can connect 16 of your chips.

The code for the SX chip would consist of 8 master I2C routines, plus

a command routine that accepts commands via the serial port and dispatches

them along the 8 I2C buses. This can be done. The whole would be command driven,

meaning each I2C bus gets serviced when a command for that bus arrives.

regards peter

 

 

 


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