On Fri, 2005-07-08 at 16:17 +0200, Wouter van Ooijen wrote:
> > If this is the case, I think there maybe a bug in Wouter's 
> > wisp628 code
> > which looks like it sets the SDATA line from the programmer to be an
> > output and sets it's state before raising the SCLK line for the first
> > time.
> 
> let me (or the list) know when you reach a verdict :)

I think I need to implement Olin's circuit to detect when the target is
driving the PGD line and check to see when it is released.  I've got a
spare PORTC pin I can use. 

I've just checked back to the 16F877A manual and it was much more
obvious what happens in that case as if shows the signal going tri-state
after the 14th bit has been sent.

Peter

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