> >> 2nd clock pulse after the start condition.  I'd want to zoom in and
> >> check the timing there is ok
> >
>
> Well, I guess that's ok then!

With the addition of 100pF to SDA the 320ns increases to 360ns. (I
just noticed that the trailing 380ns should have read 280ns, sorry for
the typo). It increases to 300ns with 100pF

I've got limited time for further testing at this stage but did try a couple
of things. F88 slave @ 4MHz IntRC, comms work in every case. @
8Mhz IntRC, of these only 107.4kHz works

I2C = 530kHz, SSPADD = h10, SDA L-H = 320ns, H-L = 280ns
I2C = 107.4kHz, SSPADD = h59, SDA L-H = 320ns, H-L = 280ns
I2C = 98.8kHz, SSPADD = h61, SDA L-H = 300ns, H-L = 260ns
I2C = 75.9kHz, SSPADD =  hFF, SDA L-H = 300ns, H-L = 260ns


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