>-----Original Message-----
>From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] 
>Sent: 06 July 2005 12:57
>To: Microcontroller discussion list - Public.
>Subject: Re: [PIC] Multiple F88 slaves on I2C buss
>
>
>Jinx wrote:
>> Sorry, should have made that clear. Top trace is SCL, next is SDA, 
>> lowest is the s/w marker (see what I mean about the doubles ?). SDA 
>> consists of address, 5 non-zero data bytes and 4 zero data 
>bytes. The 
>> second half of the SDA trace should be clear (0 data and ACKs)
>
>OK, so we finally know that the ACK was being sent on the bus. 
> The start of the second trace is interesting, so I snipped it 
>out and attached it.  The master is sending the address byte, 
>which is for address 16 of a write transfer.  The bus signals 
>themselves look good, and the first evidence of something 
>wrong is the master producing the second debug pulse. 

The image dosen't have enough resolution to say one way or the other, but the data goes high somewhere very close to the falling edge of the 2nd clock pulse after the start condition.  I'd want to zoom in and check the timing there is ok.

Regards

Mike

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