Generally one would like to understand the failure mode, in
order to ensure that you are not going to be bitten again later.

Could it be a silicon bug? e.g. divisor not providing the correct
clocks in the F88. You would think slower would be better,
but maybe there is some glicthyness in your lines.

A quick test would be to double your crystal frequency
on one side, and then the other to see if it's an
absolute time, or relative time (bit period vs Tcy) issue.

You're not sending continuous data streams are you?

Robert

Wouter van Ooijen wrote:

>>The final fix appears to be running the "100kHz" buss at > 104kHz.
>>So far nothing is going wrong at 106kHz and my code is performing
>>as it should have been two long long weeks ago
>>
>>If I wasn't so relieved I'd be dancing
> 
> 
> But do you have any idea why this fiex works (or rather: why the
> slightly lowe speed fails)?
> 
> Wouter van Ooijen
> 
> -- -------------------------------------------
> Van Ooijen Technische Informatica: www.voti.nl
> consultancy, development, PICmicro products
> docent Hogeschool van Utrecht: www.voti.nl/hvu
>  
> 
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist