In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Peter Van der Zee wrote:

Hi Keith;

I'm back, and have read your replies, but will not get back to finishing my "debug sprinkled code" for you until tomorrow.

Actually I had not read ANY of your code as I don't pretend to know SX/B adequately to be able to spot problems, but I DO know my assembler code, and how to squeeze a lot out of an SX.

Also I had expected you to be able to read what I was doing and note that the received byte was not yet outputted, and I neglected to point that out to you. Obviously, not having read your code, I had no idea of port and bit assignments nor polarities.

Regarding your post of 1:30 PM, I take issue with your statement that the ISR should fire every 2 USec.

Instead, I believe (and this is how my code is written) that the ISR should sample 3 Usec after detection of a falling edge to put it in the middle of the next cell, allowing for maximum cell timing jitter. Then subsequent ISR's must each fire in 2 USec, staying in the middle of each subsequent cell.

Each time a falling edge occurs, then the next ISR must again fire in 3 Usec. This way each falling edge "resyncs" the whole process.

Also, the maximum number of consecutive zeros read may only be three, so if 4 are detected, an "end of sequence" is assumed, and the process is restarted.

Furthermore the ISR responds to the falling edge in 60 nSec; 3 instructions at 50 MHz. so I don't know where you are getting your numbers from. Is something slow happening in the ISR under SX/B ???  Perhaps I'll do an SX/B compile on your code tomorrow and see what assembler code that produces.

If I understand the nature of the floppy's signals, then I'm pretty sure my code is correct.

I hope I don't have to write a real-time simulator for that to prove it out.

We'll see, and I'm positive we'll get to the bottom of this real quick.

Cheers till tomorrow,

Peter (pjv)

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