I wrote:
> If you need more details, I'll attempt an ASCII-art block diagram.

Actually, what I described previously is a little too simplistic -- it
assumes that at least one V/F count will occur during each I2C cycle,
which isn't general enough. What's really required is a register that
captures the counter value *except* for a few clocks after each LSB
change. This requires that the entire data value be delayed for at
least one clock.

Something like this (view with monospace font):

                        :
       V/F clock domain : I2C clock domain
                        :
           +-----+      :  +-----+      +-----+
           |     |  MSB :  |  R  |      |  R  |
           |  C  |-------->|  e  |----->|  e  |------>
           |  o  |-------->|  g  |----->|  g  |------>
           |  u  |-------->|  i  |----->|  i  |------> to I2C
           |  n  |-------->|  s  |----->|  s  |------> bus interface
           |  t  |-------->|  t  |----->|  t  |------>
           |  e  |-------->|  e  |----->|  e  |------>
  V/F  --->|> r  |-------->|  r  |--+-->|  r  |------>
 output    |     |  LSB :  |     |  |   |     |
           +-----+      :  +-----+  |   +-----+
                        :  always   |      ^ enable
                        :  enabled  |      |
                        :           |    +----+
                        :           |    |AND |<---- inhibit (low)
                        :           |    +----+     on address match
                        :           |      ^        to end of cycle
                        :           |      |
                        :           |    +----+
                        :           +--->|XNOR|<-----+
                        :           |    +----+      |
                        :           |                |
                        :           |  +---+   +---+ |
                        :           +->|D Q|-->|D Q|-+
                        :              |   |   |   |
                        :              +---+   +---+
                        :
                        : all registers and flip-flops on this
                        : side are clocked by the (intermittent)
                        : I2C clock
                        :

-- Dave Tweed
-- 
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