On June 24, 2005 05:16 pm, Jose Da Silva wrote:
> On June 24, 2005 03:19 pm, Glenn Jones wrote:
> > Hello,
> > I am working on an FPGA design which I want to have a counter which
> > counts pulses from a V/F converter. I want the counter to be read
> > out via I2C. My question is, what is the standard way of
> > accomplishing something like this because it seems to violate some
> > of the rules of synchonous logic design. How is this done in an RTC
> > (which seems to be a very analogous situation to this one)? My main
> > concern is that when the latch signal comes from the I2C address
> > match (to store the current counter value to be transfered over the
> > I2C bus), how can I ensure (at least with very high probability)
> > that the counter is not in the middle of rippling? I suppose I need
> > some sort of
> > synchronizer, but since I don't want to have to have a 3rd clock
> > source, I'm not sure what the best way to do this is.
>
> Do the same thing done for serial RX/TX type of hardware.
> Basically, you use a buffer.
> When you ask for a count via the I2C, the count is copied from the
> register to a buffer. Now you have a "snapshot" of the count. The
> buffer is read by the I2C at whatever speed the I2C runs at,
> meanwhile, the real counter is left alone to continue counting.

...I forgot to also describe "when" because of the ripple.

A safe time to read is when nothing is happening on your counter.
Suppose that your counter is +ve-edge triggered (going from 0v to 5v).
In this case, you may consider a safe time to read your counter into the 
buffer-latch would be during the -ve-edge of your V/F input clock.

Your buffer is read by the I2C at whatever speed it runs at, while the 
counter continues to count your V/F.
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist