> > Note that in a sense even an ARM has some sort of paging/banking:
> > neither 32-bit constants, nor full 32-bit data or code 
> (same thing on an
> > ARM) addresses fit into a (32 bit!) instruction. So there 
> are tricks and
> > workarounds to get a 32-bit value in a register, and to 
> address anything
> > in the 32-bit address space (but not paging/banking as we 
> know it on the
> > PICs).
> 
> The ARM branches directly and conditionally on +/-32MB using a single 
> 32bit word 

Indeed, in a (proportionally smart but absolutely large) part of its
address space.

> and indirectly on 4GB (by loading a register or immediate 
> value into the PC which is also a register).

Indeed, using one instruction + one nearby data word. So using 64 bits.
Or by having the target value in a register, but that would have taken
64 bits to get that value there.

As I said, a way to cope with the limitations of its instruction set,
although very different from the paging/banking of a PIC.

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: www.voti.nl/hvu
 

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist