> This is a somewhat false economy.  When the program
> remains small, it works well but when the program
> spills into a second bank or page or what ever, the
> cost of inter bank/page/whatever accesses is fairly
> high in program size, execution speed and especially
> complexity.  I sure do fuss with rp0 and rp1 a LOT, so
> does my compiler.  I bet an incredible about of effort
> is spent on this issue, especially tracking down
> elusive bugs.  I would not be suprised if compiler
> writers spend a lot of time trying to optimize
> twiddling those 2 bits. 

OTOH the alternative is wider instructions (more bits) and wider (or
more) registers. Even on the smaller chips that don't need them, or some
kludge to leave them out on the smaller chips (compare the old 24-bit
oriented ARM chips). 

But I think the point is: the advantage of this (paging/banking) scheme
is early in the life span of the chips, the disadvantages come later.
With a 'regular' architecture it is the other way round. So guess who
will grab the initial market, and get the benefit of high volumes? It
not 'fair', but it is how the laws of this jungle work.

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: www.voti.nl/hvu
 

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