This is a somewhat false economy. When the program remains small, it works well but when the program spills into a second bank or page or what ever, the cost of inter bank/page/whatever accesses is fairly high in program size, execution speed and especially complexity. I sure do fuss with rp0 and rp1 a LOT, so does my compiler. I bet an incredible about of effort is spent on this issue, especially tracking down elusive bugs. I would not be suprised if compiler writers spend a lot of time trying to optimize twiddling those 2 bits. Microchip is treading a well worn path. This false economy gets relearned every few years in the computer industry since the introduction of the first commercial computer. A manufacturer introduces a computer and the programmers quickly push the limits. The next generation computer has more memory to accomodate bigger programs. The manufacturer usually stresses upward compatibility and thus doesn't bite the bullet in making the architecture tuned for larger programs. A competitor comes along with an architecture more suited for the larger programs. Eventually, the company either goes away or gets smart and fixes the architecture. Look at Intel - 8086 to 80286 (64K segments, gag, whattamess). They spent countless man years building tools to help customers design around segments. Motorola and Zilog were nipping at their heels. Intel got smart and junked the 286, introducing the flat and linear 80386. Interestingly enough, it was a compiler designer that led the design of the 386 architecture. In the end, memory size was not at all a limiting cost so all that effort turned out to be wasted. The parallels are very interesting - much can be learned from that bit of history. Phil --- Wouter van Ooijen wrote: > > This is my (slightly > > educated) guess about why it exists: banking and > paging make > > the hardware > > more simple. Someone else may have some evidence > for or > > against this idea, > > but for what little bit of digital design I > remember this is > > my stand. ;) > > Main reason is that the (data or code) address field > must fit in an > instruction, an instruction has a limited size, and > this size should not > be choosen too large because the Flash is a large > part of the cost > (size) of the chip. Another: some PICs have an > address range that is > large than the register size (8 bit). ... > > Wouter van Ooijen __________________________________ Yahoo! Mail Stay connected, organized, and protected. Take the tour: http://tour.mail.yahoo.com/mailtour.html -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist