In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Coriolis wrote:

[quote="Bean (Hitt Consulting)"]
What I have been looking for is a SRAM chip that allows the address to be sent serially, has a increment pin to increment the address that was sent, and a parallal data bus. With a read speed of about 50nSec or so. I'm not worried about the write time.
Anyone know of one ? I know I can built it with multiple chips, but surely someone makes it.
 

It would be ideal for this project also.


Bean.





The closest memory I can think of is VRAM, but that has a parallel and serial [i]data[/i] access, I dont think the address is serial (though some variety of VRAM may support this). 

 

My suggestion is to use a PLD front end to perform these functions, that is the route I decided to take when I needed too many pins on the SX52 for other purposes. The address lines are driven with a counter and latch and the default action when accessing the memory (reading and writing) is to post increment the address after access is complete (the latch is updated when the SX signals memory access is complete (by sending the function NULL). So random access of any memory address follows this command list: NULL-> LOAD_ADR (data on bus loaded into low address byte) -> NEXT1 (data on bus loaded into middle address byte) -> NEXT2 (data on bus loaded into high address byte) -> READ_MEM (contents of memory on data bus) -> NULL (address is incremented), subsequent reads from sequential addresses is accomplished via READ_MEM, NULL combinations.[/quote]

---------- End of Message ----------


You can view the post on-line at:
http://forums.parallax.com/forums/default.aspx?f=7&p=1&m=76639#m76704

Need assistance? Send an email to the Forum Administrator at forumadmin@parallax.com

The Parallax Forums are powered by dotNetBB Forums, copyright 2002-2005 (http://www.dotNetBB.com)