In SX Microcontrollers, SX/B Compiler and SX-Key Tool, mebikerider wrote:

You have a number of options.

I just posted a project where an SX28 uses a 512K CMOS RAM chip by sending port C to one of 4 places - a low-8 address latch, a middle-8 address latch, a high-3 address latch, or the RAM data bus. Port B operates a 74HCT139 data selector to trigger the appropriate latch and to operate the RAM control lines. It's working great.

If you're mainly going to use the RAM serially, you could use counters, like the 12 bit CMOS 4040 (if I remember correctly), to generate any number of address bits - the SX would only have to clock one line to increment all address lines.

David

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