I understood that the edges of the wafer had worse yield that the centre?
D

Jinx wrote:
>>I know that Atmel does that as I have taken a tour of their facility
>>where they test and mark the parts.
> 
> 
> Just curious - harking back to the question of trying over-clocking
> an -04 PIC (even though it might actually be quite happy running
> at > 4MHz as a -20 reject)
> 
> How intensive is batch testing ? Say you have a bunch of micros
> made from several wafers. Presumably, ideally, each wafer and
> subsequent layers would be made of homogeneous material. So
> 
> (1) if you're working with known, controlled materials why does a
> batch or part fail to meet spec in the first place
> 
> (2) if one piece from a batch or base wafer fails, can you assume
> that the rest of that batch/wafer also will fail. Surely it can't be
> necessary to test every piece in a high-volume product
> 
> (3) therefore is a selected sample rigorously tested under all conditions
> and that assumption made, for whatever reason, for the rest of them
> 

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