> +12V ----------------+----------------------+--------
>              OPTO   |                 220  |
>   +--------+        |              +\/\/\/-+  _ /|
>   |       _|_     |/C              |       +-| | |
> INPUT     /_\ --> |               -+--| |----|_| |
>   |        |      |\E            |/C  1uF       \|
>   +-\/\/\/-+        |         +--|
>       1K            |         |  |\E
>                     |         |    ----+
>                     |         | 10K    |
>                     /     ----+-\/\/\/-+------+
>           INPUT POT \   |/E                   |
>                 10K /<--|      +----PWM INPUT |
>                     \   |\C    /              |
>                     |     |    \ PWM POT      |
>                     |     +--->/              |
>                     |          \ 10K          |
> GND -----------------+----------+--------------+-----
>
> As far as I know all the transistors are NPN (!) (BC547) The circuit
> diagram layout is a bit strange, but the idea was for the switch
> transistor to allow current to pass from the PWM input to the
> amplifier's base (plus a 10K resistor to ground) when the opto
> conducted. Have I done something terribly wrong? (Obviously I'm not
> too good at analog circuits :-)

No - you are correct that both the transistors should be NPN. Must 
have been asleep when I said otherwise ;-)
The failure to turn on when Vpwm-dc is less than about 0.7v is due to 
the second transistor base needing that much voltage to be biased on.

As I said, if it works OK for you then fine - but here is a suggested 
change which you MAY want to try once you get the basic system 
working.

Q1 = 1st transistor
Q2 = 2nd transistor
Call existing 10k = Ra

[Ca]    Electrolytic /10 uF from Q1e to Q2b.
[Rb]    68K to 100k resistor Q2b to +12v
Q2e emitter resistor to ground of 100r [Rc]
Increase 220r somewhat - say 470r to start [Rd]
[Cb]    Electrolytic ?10 uF Q2e to ground.

What this does is provide fixed DC bias for Q2 base using Ra/Rb. Base 
is about 1.5v above ground so emitter will be about 1v. 1vish across 
Rc forces ~= 10mA collector current.
This also flows in Rd so 10 mA x 470r = 5v drop so Q2c sits at about 
6v ish.
Input signal is coupled to Q2b by  Ca so DC level of PWM affects 
signal but not dc bias on Q2.

Gain of this stage is about 200 - 300 (don't ask) so signal level 
control via PWM pot may need to be lowish.

To reduce gain remove Cb when gain is ABOUT 220R/Rc - or in this case 
about 2.
DC current (which helps set power capability) and gain interact 
rather.
Having two emitter resistors with a capacitor in series with the lower 
of the two allows setting DC  current and gain semi separately.

Now play :-)



        RM

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