From: "michael brown" Well, it turns out that either the first errata item applies to my scenario (though the wording seems to indicate otherwise), or I have actually discovered a new high sleep current bug in the chip. I have the CONFIG word set to use the internal oscillator block (INTRC_IO). This means that the PIC starts at 31.25 khz. Therefore right after startup, I do this: movlw b'01110000' ; Set internal osc to 8Mhz movwf OSCCON & 0x7F The errata sheet (DS80171f) indicates that a high sleep current will occur if you: "CONDITION: FOSC<2:0> (Configuration Word Register 1) bits are configured for any oscillator selection other than the internal RC oscillator. <----- Note "other than" PROCEDURE: 1. Clock switch occurs anywhere in the application code where the internal RC oscillator is selected via the SCS bits (=9110=92). 2. Sleep mode is entered while the SCS bits are configured for the internal RC oscillator (=9110=92). Work around Before Sleep mode is entered, configure or clear the SCS bits (=9100=92) to switch back to the primary clock source that is defined by FOSC<2:0> (Configuration Word Register 1)." I don't meet the CONDITION clause because I have FOSC<2:0> set to use the INTRC (internal oscillator block). I also don't believe that the SCS bits are '10' since I specifically set them to '00' when I load OSCCON to switch to 8mhz. However, when I do the work around by doing this in the code: bsf STATUS, RP0 ; BANK 1 clrf OSCCON ; Slow way down for errata to acheive low current sleeping nop sleep nop movlw b'01110000' ; Set internal osc back to 8Mhz movwf OSCCON & 0x7F bcf STATUS, RP0 ; BANK 0 my sleep current drops to ~3uA instead of the 120uA I had been experiencing. Hallelujah So, does this look like a bug in the silicon? PS: I really wish microchip would firm up their terminology on the internal oscillator block. I quote this from the datasheet: "Throughout this data sheet, when referring specifically to a generic clock source, the term =93INTRC=94 may also be used to refer to the clock modes using the internal oscillator block. This is regardless of whether the actual frequency used is INTOSC (8 MHz), the INTOSC postscaler, or INTRC (31.25 kHz)." People considering using the 16F88 may wish to fully study the errata since the IOFS bit (which is supposed to indicate clock stability after a switch in speed) is worthless according to item 2. Item 3 in the errata should be particularly interesting. > Hello all, > > I've been tinkering with sleep mode on my data logger project and I seem > to be having some trouble. I can't get the sleep current on the PIC to > less than 120uA while it is sleeping, it should be less than 5uA. I > don't have the PORTB pull-ups on, nor do I have the comparators or their > Vref on. No floating input pins, no "loaded" output pins. I've tried > turning the ADC completely off but that makes virtually no difference > (just like the datasheet indicates). No ADC conversions are taking > place while I sleep. I'm using the internal oscillator at 8Mhz. MCLR > is disabled and tied to ground. Brown out is disabled and watch dog is > disabled. No timers are being used. I wake up with RB0 interrupts once > per second and that's all working perfectly. > > I'm measuring current at the Vcc pin of the PIC. My meter is not the > greatest in the world, but it seems capable of giving me reasonable > readings at lower currents than 120uA. Any ideas as to what I have > missed? The only things I specifically enabled are: the ADC, RB0 ints, > the UART in async mode. > > --=20 > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist