I guess age is showing, but I am puzzled as to why ANY race condition 
can exist
in the Q7 unregistered output stage.

It IS true that propagation delays will sum up and eventually cause the 
serial clock
speed to  require being slowed down, that does not consiitute a "race". 
On the 595,
nothing changes on the output until another, unique clock (REG CLK) is 
toggled.

I've been using several consecutive stages of HC and LV595s without the 
slightest
problem for many years, but as more stages are added, the serial 
(transfer) clock
has to be slowed, that's all I have to do.

Flames expected.

--Bob

Ian Chapman wrote:

>res0qrqr@verizon.net wrote:
>  
>
>>There was a very comprehensive thread here perhaps four or five years
>>back on this topic.
>>    
>>
>
>I remember that thread.  I haven't found a link to it, though.
>
>  
>
>>I think (?) the general conclusion was that the 74xx595 lacks a gate
>>internally which would be needed to prevent a race condition when the
>>chips are daisy-chained as you are doing.
>>    
>>
>
>The potential problem is that the Q7' (expand) output from the internal
>shift register in the 74xx595 changes state on the same (rising) edge of
>the clock as the serial data input.  This may cause timing problems with
>chains of devices depending on how the clock is distributed.
>
>The comparable device in the CMOS family (the 4094) enables this problem
>to be avoided.  It has a second expand output (QS2) which is delayed by
>half a clock cycle through an extra flip-flop clocked on the opposite
>(falling) edge of the serial clock.  Unfortunately, the 4094 isn't pin-
>compatible with the '595 and doesn't have an asynchronous clear input
>for the shift register which may be needed in some applications.
>
>I would hope that some of the newer '595-like devices with high-current
>output stages have learnt from this issue.
>  
>


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