At 09:40 PM 3/1/2005, Marcel Duchamp wrote:
>Brusque,
>
>It sounds like maybe you have propagation time problems with your data lines.
>
>If your chips have all their clock lines tied together, this is what 
>happens.  The last chip in line (nr 6) gets its clock at the same time as 
>the first chip.  But it doesn't get any data on its data input until the 
>data has flowed through all the previous 5 chips.  At slow clock rates, 
>this is not a problem.  At high clock rates, you begin to have a race 
>condition.  Eventually, the clocks come and go before the data gets there.

This isn't really a race condition, just clock skew.
A race would be where the gates could oscillate for short periods.

But in general I think you're right, it's a timing problem where clock and 
data are getting further and further out of sync, or maybe a ringing on the 
clock line at the end, that doesn't show up closer to the driving end.

Hanging a good two channel scope on the end should resolve that question.

This is one where a logic analyzer would be of rather dubious help.


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