Dear Russel,


At 02.11 2005.02.12 +1300, you wrote:
>>This circuit really seems to ensure full swing (I've been
>>able to successfully test this aspect) but, will it give
>>maximum speed? This is may concern.
>
>The circuit you drew with 2 transistors should work to 100 kbps plus provided you change the 100R to 1k to 10k.
>The problem you had before with low voltage swing was due (probably) to attempting to drive too high a current with the opto for the avail;able drive. Typically you get an output current of 10% of the input current maximum. )Check data sheet for your opto).

It's not much better than that.. in fact. But I didn't really understand this point of the data sheet, hence my failure.


>The following circuit (use fixed width font) should work and uses only 1 transistor. I use something similar at 100 kHz+ as a FET gate driver.
>
>
>
>       RM
>
>
>       ,-----------------.---------------- DTR
>       |                 |           (low, i.e. +12V)
>       |                 |
>       \ 1k - 10k        |
>       /                 C
>       \          ,---- B    NPN (BC547)
>       /          |      E
>       \          |      |
>       |          |      |
>       |    10K   |      |
>5 ------*----------*      *---------------- RX
> 4N25             |      |
>4 ------.          |-|<|--. 1N4148
>       |
>       |
>       |
>       |
>       |
>       |
>       |
>       '--------------------------------- RTS
>                                    (high, i.e. -12V)

Ingenious, brilliant!

I've been trying ways to shut off the transistor when the opto was saturated, but didn't find a way. It's in your schematic above. :)

Speaking of pure performance and high/low simmetry, do you think that the PNP/NPN circuit may perform a bit better than the circuit above?
Number of components-wise they're fairly similar anyway (1 more transistor versus 1 more diode and 1 more resistor).

What I liked most of the PNP/NPN approach was its simmetry.

Greets to NZ,
TPM

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