Dear all, My servos actually worked with a 250 Hz period (strange according to the specs) at 4 MHz and I have the maximum resolution of 14 bits though I can only use 10... My problem is that when I activate the second CCP channel the overflow interrupts are getting confused and as a result, my first servo works perfectly but the second one has a delay at the beginning and then I get a duty cycle of 70us. Can someone check my code please? ;############################################################################ ; Author : Antonis Iliopoulos ; ; Date : 03 / 02 / 05 ; ; Title: 2 CCP channels with fixed PWMs ; ; ; ; Description: The following program was created to produce a PWM signal through the ; ; CCP channel on RC2 that will set the motor to a fixed position by entering the appropriate ;value in CCPR1L and CCP1 CON and does the same for CCP in RC1 by entering the ;appropriate value in CCPR2L and CCP2 CON ;############################################################################ list p=16f777 include ;------------------------------------------------------------ ;internal oscillator at 4 MHz ;------------------------------------------------------------ #define ccp1 portc,2 #define ccp2 portc,1 org 0x000 banksel OSCCON ; got to appropriate bank movlw b'01100000' ;Device is running from INTRC as a secondary system clock movwf OSCCON ; T1OSC is used for system clock at a stable frequency of 4MHz movlw b'00000000' ;with 1 set inputs and with 0 set outputs movwf trisb^0x080 ; portB is all outputs ;bcf trisc,2 ;We clear ccp1 pin to make it output reference: 14.5 ;bcf status,rp0 ;bank0 ;bcf ccp1 ;we set the ccp1 pin low BANKSEL TRISC ;GO TO THE APPROPRIATE BANK bcf trisc,1 ;We clear ccp2 pin to make it output reference: 14.5 bcf status,rp0 ;bank0 bcf ccp2 ;we set the ccp2 pin low bcf status,rp0 bcf intcon,7 ;disable global interrupts bcf intcon,6 ;disable peripheral interrupts bsf status,rp0 ;bank 1 bcf pie1,1 ;disable timer 2 interrupts bcf pie1,2 ;disable ccp1 interrupts bcf pie2,0 ;disable ccp2 interrupt banksel pir1 ;GO TO THE APPROPRIATE BANK clrf pir1 ;No TMR2 to PR2 Match occured bcf status,rp0 ;BANK 0 clrf ccp1con ;ccp1 module off clrf ccp2con ;ccp2 module off bsf status,rp0 bcf status,rp1 ;bank 1 movlw b'11111111' ; Period of approximately 250Hz movwf pr2 ;load period register bcf status,rp0 bcf status,rp1 ;bank 0 bsf ccp1con,5 ;set bit 1 of duty cycle reg bcf ccp1con,4 ;clear bit 0 of duty cycle reg - pwm movlw b'00101011' ;DUTY CYCLE movwf ccpr1l ;bits 9-2 of duty cycle ; Duty cycle for pwm 1 = '0010101110' bsf ccp2con,5 ;set bit 1 of duty cycle reg bcf ccp2con,4 ;clear bit 0 of duty cycle reg - pwm movlw b'10001010' ;DUTY CYCLE movwf ccpr2l ;bits 9-2 of duty cycle ; Duty cycle for pwm2 = '1000101010' bcf status,rp0 bcf status,rp1 ;bank 0 movlw b'00000011' ;prescaler = 0 to be 1, 1 to divide by 4, 1x for 16 movwf t2con ; clrf tmr2 ;clear tmr2 movlw b'00001100' ;ccp1 pwm mode, ccp1 module on movwf ccp1con movlw b'00001100' ;ccp2 pwm mode, ccp2 module on movwf ccp2con banksel t2con ; go to appropriate bank bsf t2con,2 ;tmr2 on end regards Antonis --------------------------------- ALL-NEW Yahoo! Messenger - all new features - even more fun! -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist