Shawn Tan Ser Ngiap wrote:
> The sampling point baud signals (call it baud_clk) are divided from a
> main clock... This results in a regular signal... Let's imagine a train
> of thin square impulses...

The point you seem to be missing is that this clock you call BAUD_CLK is
running at a multiple (usually 16) of the baud rate.

> What happens is this.. When a start-bit is detected, it will start the
> FSM (which i assume was in an IDLE state before this), and start
> shifting the bits into the receiver register.. But the baud_clk train
> remains constant, before and after the byte is moved in...

Note that what you call "start the FSM" is exactly the synchronizing step
we've all be talking about.  This happens at the resolution of your BAUD_CLK
clock, not the actual baud rate.  If BAUD_CLK frequency is 16x the baud
rate, then the FSM is synched to the leading edge of the incoming byte to
within 1/16 bit.

> To me, that indicates a fixed sampling period.. whether they use a
> single point or multiple voting points, the period is still fixed..

The period is fixed with a byte, but the phase is re-adjusted each byte by
synchronizing it with the leading edge of the start bit.  That's what the
start bit is for.  That's why this is call "asynchronous".


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